Cache memory is based on a premise that programs reuse the same instructions and data. Cache memory comprises one or more levels of dedicated high-speed memory holding recently accessed data, designed to speed up subsequent access to the same data.
A cache transparently stores data as entries so that future requests for that data can be served faster. The cache monitors requests for data to see if requested data has already been stored in the cache. If the data had indeed been stored in the cache, the data is delivered with to the processor from the cache. Each cache entry is typically accessed by an address tag and index.
A cache can perform functions requiring two different types of memory, data memory and tag memory. Data memory actually stores data representing data in main memory. Tag memory, or tag RAM, stores data that determines which memory locations are actually stored in the cache. In general, the tag memory contains a plurality of entries corresponding to the entries of the data cache. Each entry is indexed by some number of least significant bits of the address, with the tag entry itself containing the most significant bits of the memory location which is stored in the corresponding data cache entry, typically the address of the main memory location associated with a cache entry.
A cache address can be specified simply by index. A tag is kept to allow the cache to translate from a cache address (tag, index) to a unique system address. A cache hit means that a system tried to access an address, and a matching cache block (index, and matching tag) was available in cache. In a cache miss, the system tries to access an address, and there is no matching cache block.
Caches are typical classified as direct mapped cache of associative cache. In a direct mapped cache each main memory address maps to a unique cache location. In fully associative cache, any main memory address can be associated in any cache location. In set associative cache each address tag corresponds to a set of cache locations.
The number of address tags required in a cache is proportional to the size of the cache. Larger physical memory spaces require more address bits and correspondingly wider memory to store each address tag.
A memory address can be split into a tag, a index and a block offset. The index describes the cache row where data is stored. The block offset specifies the desired data within the cache row. The tag contains part of the address of the actual data fetched from the main memory.